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PIC18F2450/4450
DS39760A-page 100
Advance Information
2006 Microchip Technology Inc.
TABLE 9-1:
PORTA I/O SUMMARY
TABLE 9-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Pin
Function
TRIS
Setting
I/O
I/O Type
Description
RA0/AN0
RA0
0
OUT
DIG
LATA<0> data output; not affected by analog input.
1
IN
TTL
PORTA<0> data input; disabled when analog input enabled.
AN0
1
IN
ANA
A/D input channel 0. Default configuration on POR; does not affect
digital output.
RA1/AN1
RA1
0
OUT
DIG
LATA<1> data output; not affected by analog input.
1
IN
TTL
PORTA<1> data input; reads ‘0’ on POR.
AN1
1
IN
ANA
A/D input channel 1. Default configuration on POR; does not affect
digital output.
RA2/AN2/
VREF-
RA2
0
OUT
DIG
LATA<2> data output; not affected by analog input.
1
IN
TTL
PORTA<2> data input. Disabled when analog functions enabled.
AN2
1
IN
ANA
A/D input channel 2. Default configuration on POR; not affected by
analog output.
VREF-
1
IN
ANA
A/D voltage reference low input.
RA3/AN3/
VREF+
RA3
0
OUT
DIG
LATA<3> data output; not affected by analog input.
1
IN
TTL
PORTA<3> data input; disabled when analog input enabled.
AN3
1
IN
ANA
A/D input channel 3. Default configuration on POR.
VREF+
1
IN
ANA
A/D voltage reference high input.
RA4/T0CKI/
RCV
RA4
0
OUT
DIG
LATA<4> data output; not affected by analog input.
1
IN
ST
PORTA<4> data input; disabled when analog input enabled.
T0CKI
1
IN
ST
Timer0 clock input.
RCV
x
IN
TTL
External USB transceiver RCV input.
RA5/AN4/
HLVDIN
RA5
0
OUT
DIG
LATA<5> data output; not affected by analog input.
1
IN
TTL
PORTA<5> data input; disabled when analog input enabled.
AN4
1
IN
ANA
A/D input channel 4. Default configuration on POR.
HLVDIN
1
IN
ANA
High/Low-Voltage Detect external trip point input.
OSC2/CLKO/
RA6
OSC2
x
OUT
ANA
Main oscillator feedback output connection (all XT and HS modes).
CLKO
x
OUT
DIG
System cycle clock output (FOSC/4); available in EC, ECPLL and
INTCKO modes.
RA6
0
OUT
DIG
LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
1
IN
TTL
PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTA
—RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
LATA
—LATA6(1)
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
TRISA
—
TRISA6(1)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
ADCON1
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
UCON
—
PPBRST
SE0
PKTDIS
USBEN
RESUME SUSPND
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
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